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overview the LC74411N and LC74411Ne are digital processing controllers for pip (picture-in-picture) systems in tv sets and vcrs. these ics incorporate three circuits, a multiplexed a/d converter, field memory, and a d/a converter, to implement the pip digital processing block in a single chip. features ?horizontal resolution: 450 pixels* single-chip implementation of the three circuits required in a pip digital processing block: a/d converter, field memory, and d/a converter circuits high image quality provided by vertical filtering ? 2 c bus adopted built-in pll circuit (requires an external low-pass filter) supports ntsc and pal, tv and vcr applications, and multi-format (ntsc and pal) applications. external control function 8-bit d/a converter (pwm type): 6 pins general-purpose ports: 8 pins sub-screen specifications display on/off, frame/no frame, frame color switching, wipe function display position - specifiable as an 8-bit value for each of the horizontal and vertical directions. size vertical reduction: 1/3, 1/4 horizontal reduction: 1/3, 1/4 the horizontal size can be adjusted by adjusting the pll divisor the display area vertical and horizontal positions can be varied independently. horizontal resolution (y signal): about 190 dots quantization: 6 bits operating supply voltage LC74411Ne : 5 v ?% LC74411N : 5 v ?0% package LC74411Ne : qfp64e LC74411N : dip64s package dimensions unit: mm 3071-dip64s unit: mm 3159-qfp64e cmos lsi ordering number : en * 5519a 93196ha (ot) no. 5519-1/14 preliminary sanyo: dip64s [LC74411N] sanyo: qip64e [LC74411Ne] sanyo electric co.,ltd. semiconductor bussiness headquarters tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110 japan pip controller LC74411N, LC74411Ne note: when the main screen synchronization pll uses the standard value (pll4 : 0 = 10110) d/a clock y 11.6 mhz r-y 2.9 mhz b-y 2.9 mhz
pin assignments no. 5519- 2 /14 LC74411N, LC74411Ne
block diagram no. 5519- 3 /14 LC74411N, LC74411Ne
LC74411N and LC74411Ne based pip system function overview reduction sizes ?vertical : 1/3, 1/4; the vertical filter coefficient can be selected. ?horizontal : 1/3, 1/4; variable at the pll. still image ?field still image display position ?eight bits in each of the vertical and horizontal directions frame ?frame or no frame can be selected. ?frame types differ according to the insertion method pin frame : a pin output that goes high at the frame position (for frame insertion by the application) dac frame : frame overlapped onto the image signal. four bits for each of the y, r-y, and b-y signals. wipe ?supports eleven different types of wipe. blanking size ?the vertical and horizontal directions can be specified independently (6 bits each) ?eleven form specification types memory clear ?the image data written to memory can be set to a fixed value. ?either 25% white or blue can be selected. wide-aspect-ratio tv support ?aspect compensation function support for ntsc, pal, and multi-format systems external control function using the i 2 c bus ?incorporates six on-chip 8-bit d/a converter circuits ?provides eight general-purpose port pins. wide range of settings and adjustments ?sub-screen displacement, color shifting, and other settings can be adjusted using the i 2 c bus. no. 5519- 4 /14 LC74411N, LC74411Ne
sub-screen size the vertical and horizontal directions can be controlled independently. vertical size ?1/3: three scan lines are compressed to one. ?1/4: four scan lines are compressed to one. horizontal size ?1/3: a/d clock : d/a clock = 1:3 ?1/4: a/d clock : d/a clock = 1:4 when 1/4 compression is used, the output data will be 3/4 of 1/3 of the input data. ?aspect ratio correction function the horizontal size is adjusted by changing the vco frequency (system clock). this frequency can be changed from ?0% to +30%. wipe function the wtop, wbot, wleft, and wright operations can be specified independently. display area function this function controls an area to be blanked. the vertical and horizontal directions can be set independently. the operating mode is set using the wipe function wtop, wbot, wleft, and wright parameters. no. 5519- 5 /14 LC74411N, LC74411Ne
application examples ?exclusion of the masked area from a letterbox screen ?small display minimizes the hidden sections of the main screen. internal control registers 0: these bits must be set to 0. no. 5519- 6 /14 LC74411N, LC74411Ne bit msb lsb function address 7 6 5 4 3 2 1 0 00h sby stl nt/pal d-blue d-fix fild vdf-c0 pout mode settings 01h vp7 vp6 vp5 vp4 vp3 vp2 vp1 vp0 vertical display position 02h hp7 hp6 hp5 hp4 hp3 hp2 hp1 hp0 horizontal display position 03h 0 size-v size-h dafrm yfc5 yfc4 yfc3 yfc2 sub-screen size, frame color 04h rfc5 rfc4 rfc3 rfc2 bfc5 bfc4 bfc3 bfc2 frame color 05h 0 0 0 pll4 pll3 pll2 pll1 pll0 pll value 06h php-m php-s wpe wp-mod wtop wbot wleft wright wipe 07h 0 0 vbs5 vbs4 vbs3 vbs2 vbs1 vbs0 vertical display range 08h 0 0 hbs5 hbs4 hbs3 hbs2 hbs1 hbs0 horizontal display range 09h v-blk h-blk cl-aj1 cl-aj0 wv-aj1 wv-aj0 wh-aj1 wh-aj0 fine adjustment 0ah 0 yc-aj2 yc-aj1 yc-aj0 ycfaj1 ycfaj0 fm-aj1 fm-aj0 fine adjustment 0bh dac1-7 dac1-6 dac1-5 dac1-4 dac1-3 dac1-2 dac1-1 dac1-0 pwmdac 0ch dac2-7 dac2-6 dac2-5 dac2-4 dac2-3 dac2-2 dac2-1 dac2-0 pwmdac 0dh dac3-7 dac3-6 dac3-5 dac3-4 dac3-3 dac3-2 dac3-1 dac3-0 pwmdac 0eh dac4-7 dac4-6 dac4-5 dac4-4 dac4-3 dac4-2 dac4-1 dac4-0 pwmdac 0fh dac5-7 dac5-6 dac5-5 dac5-4 dac5-3 dac5-2 dac5-1 dac5-0 pwmdac 10h dac6-7 dac6-6 dac6-5 dac6-4 dac6-3 dac6-2 dac6-1 dac6-0 pwmdac 11h port7 port6 port5 port4 port3 port2 port1 port0 general-purpose ports
register data overview no. 5519- 7 /14 LC74411N, LC74411Ne address register notes sby standby mode (the pll circuit operates.) stl still image (writes to internal memory are stopped.) nt/pal format selection (h: ntsc, l:pal) 00h d-blue memory clear data selection (valid when d-fix = 1) (h: blue, l: gray) d-fix memory clear (holds the data written to memory at a fixed value.) fild field display selection vdf-co vertical filter coefficient selection pout sub-screen display on/off 01h vp7 to 0 sub-screen vertical position 02h hp7 to 0 sub-screen horizontal position size-v vertical compression specification h: 1/4, l: 1/3 03h size-h horizontal compression specification h: 1/4, l: 1/3 dafrm d/a converter frame on/off yfc5 to 2 d/a converter frame color (y) 04h rfc5 to 2 d/a converter frame color (r-y) bfc5 to 2 d/a converter frame color (b-y) 05h pll4 to 0 pll divisor value (the standard value is 10110.) php-m, s field discrimination inversion/noninversion 06h wpe wipe or display area function enable wp-mod wipe or display area function selection (h: wipe) wtop to wright wipe or display area function format specification 07h vbs5 to 0 display area range setting (vertical) 08h hbs5 to 0 display area range setting (horizontal) v-blk, h-blk d/a converter frame output range specification (normally set to 00b) 09h cl-aj1, 0 a/d converter clamping potential adjustment (can be monitored from the clamp pin.) wv-aj1, 0 write vertical direction adjustment wh-aj1, 0 write horizontal direction adjustment yc-aj2 to 0 c phase (with respect to y) adjustment 0ah ycfaj1, 0 d/a converter frame c phase (with respect to y) adjustment fm-aj1, 0 d/a converter frame left/right width adjustment 0bh dac1-7 to 0 external control d/a converter (8-bit pwm) data 0ch dac2-7 to 0 external control d/a converter (8-bit pwm) data 0dh dac3-7 to 0 external control d/a converter (8-bit pwm) data 0eh dac4-7 to 0 external control d/a converter (8-bit pwm) data 0fh dac5-7 to 0 external control d/a converter (8-bit pwm) data 10h dac6-7 to 0 external control d/a converter (8-bit pwm) data 11h port7 to 0 data for the general-purpose output ports
pin functions notes: the 64e pin numbers refer to the LC74411Ne and the 64s pin numbers refer to the LC74411N. the letter "s" in an inverter indicates schmitt input characteristics. no. 5519- 8 /14 LC74411N, LC74411Ne pin no. pin i/o connection function circuit type 64e 64s 13 21 res i initialization circuit reset 45 53 v-m i main screen vertical synchronizing signal (negative polarity) 44 52 h-m i synchronization separation main screen horizontal synchronizing signal (negative polarity) 43 51 v-s i circuit ic sub-screen vertical synchronizing signal (negative polarity) 42 50 h-s i sub-screen horizontal synchronizing signal (negative polarity) 14 22 scl i microcontroller serial clock 15 23 sda i/o microcontroller serial data 16 24 addr0 i dv ss must be connected to v ss in normal operation. 17 25 addr1 i dv ss 19 27 port0 o 20 28 port1 o 21 29 port2 o 22 30 port3 o general-purpose ports 23 31 port4 o 24 32 port5 o 25 33 port6 o 26 34 port7 o 27 35 d/a1 o 28 36 d/a2 o 29 37 d/a3 o pwm d/a converter outputs 30 38 d/a4 o 31 39 d/a5 o 32 d/a6 o 36 44 frame o analog circuits frame pulse output 35 43 sout o analog circuits main/sub-screen switching signal 34 42 sout2 o 38 46 nc no connection 39 47 nc no connection 41 49 dv dd power supply digital system power supply 40 48 dv ss ground digital system power supply 64 8 ya-in i analog circuits sub-screen analog input (y) 63 7 ra-in i analog circuits sub-screen analog input (r-y) 62 6 ba-in i analog circuits sub-screen analog input (b-y) 61 5 lvl-in i preset voltage 37 45 clamp o a/d converter clamp pulse for use by user monitoring circuits continued on next page.
no. 5519- 9 /14 LC74411N, LC74411Ne pin no. pin i/o connection function circuit type 64e 64s 60 4 v rh1 power supply or vrh2 low-pass filter 59 3 v rh2 open or vrh1 low-pass filter 58 2 v rm capacitor oscillator range setting resistor 57 1 v rb capacitor and v ref power supply 1 9 adv dd power supply ground 2 10 adv ss ground 54 62 ya-out o analog circuits sub-screen digital analog output (y) 53 61 ra-out o analog circuits sub-screen digital analog output (r-y) 52 60 ba-out o analog circuits sub-screen digital analog output (b-y) 51 59 v ref i vrb d/a converter analog setting pin 50 58 bias capacitor 55 63 dav dd power supply analog system power supply (d/a converter) 56 64 dav ss ground 10 18 cp-m o low-pass filter charge pump output 11 19 fc-m i low-pass filter oscillator control voltage input 8 16 r-m oscillator range setting resistor 9 17 v dd -m power supply vco power supply 12 20 v ss -m ground 5 13 cp-s o low-pass filter charge pump output 4 12 fc-s i low-pass filter oscillator control voltage input 7 15 r-s oscillator range setting resistor 6 14 v dd -s power supply vco power supply 3 11 v ss -s ground 49 57 test0 i 48 56 test1 i 47 55 test2 i dv ss testing (these pins must connected to dv ss .) 46 54 test3 i 33 41 test4 i 18 26 test5 i parameter symbol conditions ratings unit maximum supply voltage v dd max ?.3 to +7.0 v maximum input voltage v in max ?.3 to v dd +0.3 v maximum output voltage v out max ?.3 to v dd +0.3 v allowable power dissipation pd max LC74411Ne 550 mw LC74411N 600 mw operating temperature topr ?0 to +70 c storage temperature tstg ?5 to +125 c specifications absolute maximum ratings at ta = 25 2 c, v ss = 0 v allowable operating ranges at ta = ?0 to +70 c, v ss = 0 v parameter symbol conditions min typ max unit supply voltage v dd LC74411Ne 4.75 5.0 5.25 v LC74411N 4.5 5.0 5.5 v digital input high-level voltage v ih 0.7v dd v digital input low-level voltage v il 0.3v dd v analog input voltage the ya-in, ra-in, and ba-in pins adv dd -v rb vp-p reference voltage v ref 2.7 0.8v dd v dd v continued from preceding page.
no. 5519- 10 /14 LC74411N, LC74411Ne electrical characteristics at ta = 25 2 c, v dd = 5 v 5% (LC74411Ne), v dd = 5 v 10% (LC74411N), v ss = 0 v parameter symbol conditions min typ max unit output high-level voltage v oh1 i oh = ? ma, the cp-m and cp-s pins v dd ? v v oh2 i oh = ? ma, pins other than cp-m and cp-s v dd ? v v ol1 i ol = 1 ma, the cp-m and cp-s pins 1.0 v output low-level voltage v ol2 i ol = 3 ma, the sda pin 0.4 v v ol3 i ol = 2 ma, pins other than the pins mentioned above 0.4 v quiescent current drain i dd st res = v ss , dc pin inputs, no output loads 10 a reference voltage (m) v rm when v rh1 is connected to adv dd 0.9v dd v reference voltage (b) v rb when v rh1 is connected to adv dd 0.8v dd v input leakage current i lk v i = v dd , v ss ? +1 a output leakage current i oz v i = v dd, v ss ; the cp-m and cp-s pins ? +1 a d/a converter output resistance r da 300 switching characteristics at ta = 25 2 c, v dd = 5 v 5% (LC74411Ne), v dd = 5 v 10% (LC74411N), v ss = 0 v parameter symbol conditions min typ max unit vertical synchronizing signal pulse width t vw 1 s rise time t vr 300 ns fall time t vf 300 ns horizontal synchronizing signal pulse width t hw 1 s rise time t hr 300 ns fall time t hf 300 ns i 2 c timing scl frequency t scl 100 khz bus release time t buf 4.7 s start/hold t hd sta 4.0 s scl low period t low 4.7 s scl high period t high 4.0 s data hold time t hd dat 0 s data setup time t su dat 250 ns rise time t r 1000 ns fall time t f 300 ns stop setup time t su sto 4.0 s
sub-screen digital processing specifications no. 5519- 11 /14 LC74411N, LC74411Ne item ntsc (f h = 15734hz) pal (f h = 15625hz) order y, r?, y, b?, y, ? y, ? frequency 480 f h f t (mhz) 7.552 7.500 y only 240 f h a/d converter sampling f ty 3.776 3.750 r-y only 60 f h f tr 0.944 0.938 b-y only 60 f h f tb 0.944 0.938 number of bits in quantization 6 bits y signal 736 f h f cy 11.58 11.50 d/a converter clock r-y signal 184 f h (mhz) * 1 f cr 2.895 2.875 b-y signal 184 f h f cb 2.895 2.875 number of horizontal bits 288 y only 192 write r-y only 48 b-y only 48 number of vertical lines 73 85 number of horizontal bits 268 y only 180 readout display * 2 r-y only 44 b-y only 44 number of vertical lines 72 84 note: 1. when the pll divisor has its standard value (pll4:0 = 10110). 2. target values are shown. (the number of horizontal bits varies with, for example, the frame width adjustment.) initialization (1) res pin: reset the res pin must be held low when power is first applied with the timing shown in the figure. (2) internal control registers after a reset, the chip goes to the standby state (sby = high). when developing the microcontroller software, that software must be designed so that it transmits data for all registers. also note that data values of zero (0) must be sent for the control registers that have ??entries in the control register table.
i 2 c control data format data 1 is stored at register address a1. data 2 is stored at register address a1 + 1, i.e., the address given by incrementing a1. if the address exceeds 11h, it wraps to 00h. slave address: synchronizing signal input ?sync separation the LC74411N and LC74411Ne require sync separated (including afc processing) v and h signals for both the main and sub-screen. since v is used for field discrimination and h is used as the pll reference signal, these signals must be provided reliably. ? the h-m and h-s pin inputs are assumed to be delayed about 1 s from the video signal? horizontal synchronizing signal and set to standard values. ? equalizing pulses must be excluded. ?since noise on the synchronizing signal will disrupt the display, these lines should be placed carefully. ? if the synchronizing signal is unstable, the sub-screen display may be disrupted. we recommend turning off sub- screen display in such cases. ?field discrimination circuit since the circuit discriminates based on the phase difference between the falling edges of the h and l signals, these signals must be provided with the timing shown in the figure below. no. 5519- 12 /14 LC74411N, LC74411Ne a6 a5 a4 a3 a2 a1 a0 r/w 0 0 1 0 0 1 1 0
clamp pulses ?a/d converter clamping since clamp pulses are output to the built-in a/d converter with the timing shown in the figure below, they are set up to fall in the pedestal range. the clamp pulses can be monitored at the clamp pin. on a reset or in standby mode, the h-s input signal becomes positive polarity and is output without change. ?d/a converter clamp external control output blanking no. 5519- 13 /14 LC74411N, LC74411Ne
no. 5519- 14 /14 LC74411N, LC74411Ne this catalog provides information as of september, 1996. specifications and information herein are subject to change without notice. n no products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. n anyone purchasing any products described or contained herein for an above-mentioned use shall: accept full responsibility and indemnify and defend sanyo electric co., ltd., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on sanyo electric co., ltd., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. n information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

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